In a Spread ALOHA receiver, when the received signal is a linear combination of the transmitted signals the detection of multiple overlapping packets is simplified. In the present invention, equations are derived that describe a QAM modulation and demodulation process in order to specify a common notation to be used in the network design. In the case of a single transmitter the derived equations are well known. For the case of a Spread ALOHA multiple access channel however, interest lies in the simultaneous reception of many overlapping signals. The problem does not appear to have been treated in the literature.
A receiver for spread bit packet signal transmissions has an input line with a QAM modulator connected thereto. The QAM modulator has a splitter connected to the input line for separating the input into first and second paired inputs. First and second multipliers are connected to the first and second pair inputs. A numerically controlled oscillator is connected to the first multiplier. A 90xc2x0 phase shifter is connected to the numerically controlled oscillator and is connected to the second multiplier. First and second output lines are connected to the first and second multipliers. First and second low pass filters are connected to the first and second output lines for removing high frequencies from the outputs. First and second demodulated signal lines are connected to outputs of the first and second low pass filters, and first and second despreading filters are connected to the first and second demodulated signal lines. First and second despread signal lines are connected to outputs of the first and second despreading filters. First and second pairs of synchronization matched filters are connected to the first and second despread signal lines for producing packet synchronization sequence outputs.
A preferred method of information detection in a single spreading sequence receiver comprises receiving packet and chip signals in QAM modulated carrier wave signals with in-line and quadrature components. The received signals are supplied to first and second multipliers. Output is supplied from a numerically controlled oscillator to the first multiplier and to a 90xc2x0 phase shifter. An output is supplied from the 90xc2x0 phase shifter to the second multiplier. Output signals are supplied from the first and second multipliers to first and second low pass filters, and high frequency signals are removed in the low pass filters. First and second outputs are provided from the first and second low pass filters to first and second despreaders. First and second despread signals are provided from output of the first and second despreaders to inputs of first and second pairs of synchronization filters.
In one preferred embodiment, inputs of first and second synchronization filters are connected in parallel and the first despread signal is supplied from the first despreader to the inputs of the first and second synchronization filters. Second and third synchronization filters are connected in parallel to an output of the second despreader. Despread signals are supplied from the output of the second despreader to inputs of the third and fourth synchronization filters. Outputs of the first and third synchronization filters are supplied to a first adder. Outputs of the second and fourth sychronization filters are supplied to a second adder. An output of the first adder and an output of the second adder are squared, and squared outputs from the first and second squarers are added in a third adder. A threshold of an output from the third adder is detected as a start of a packet.
These and further and other objects and features of the invention are apparent in the disclosure, which includes the above and ongoing written specification, with the claims and the drawings.